Superscalar processors that operate under an out-of-order execution model have improved their performance by allowing instructions to execute in parallel. Most instructions with no write-read dependents can be executed without obeying the order in which they are dispatched. With multiple functional units in a superscalar processor, out-of-order execution has increased the number of instructions processed per unit cycle. However, there are instructions and event handling operations in the processor that have not taken advantage of the out-of-order execution model. Most of the "context synchronizing" instructions ("CSI") and interrupts fall into this category. For example, for the processor to enter an interrupt service routine, the current approach is to wait for completion of all instructions dispatched prior to the subroutine entry. Likewise, the same approach applies to MTSPR (move to special register) instructions that modify special purpose registers, SC (system call) instructions that handle system calls, MTMSR (move to machine state register) instructions that modify the machine status, RFI (return from interrupt) instructions that are executed when an interrupt service routine ends, and ISYNC (instruction synchronization) instructions.
Traditional implementations wait for all prior dispatch instructions to complete before starting to execute the above-noted instructions or to process the events. The reason for the traditional implementation is partly due to the architecture definition and the current state of art in handling instruction completion. The architecture definition requires a CSI or event to begin after prior instructions "appear" to have completed. All exceptions generated by these prior instructions have to be handled before the start of a CSI. In the current implementation of various PowerPC processors that support out-of-order executions, all instructions dispatched are saved in a "completion buffer" which is a first-in-first-out buffer, and the completion of an instruction in the instruction buffer requires the result (if there is one) of the instruction to be deposited in the target register or sent to the memory subsystem, and the instruction does not generate an exception. For these reasons, the current implementation of CSI instructions and events holds off the start of these instructions or events until all prior instructions in the completion buffer have actually completed.
As a result of the foregoing, there is a need in the art for an improved implementation of instruction completion handling wherein CSI instructions and interrupt events are allowed to begin before all prior instructions have deposited their result in the target registers. By doing so, the processor will be allowed to increase its degree of concurrent execution of instructions.